1. Field of the Invention
The invention pertains to minicomputer systems and more particularly to a minicomputer system having a megabus with a plurality of processors, memories and input/output (I/O) units and including logic for capturing every megabus cycle that appears on the system.
2. Description of the Prior Art
In a system having a plurality of devices coupled over a common bus, an orderly system must be provided by which bidirectional transfer of information is provided between such devices. This problem becomes more complicated when such devices include, for example, one or more data processors, one or more memory units, and various types of peripheral devices.
Various methods and apparatus are known in the prior art for interconnecting such a system. Such prior art systems range from those having common data bus paths to those which have special paths between various devices. Some systems also may include capability for either synchronous or asynchronous operation in combination with the bus type. Some such systems require the data processing control of any data transfers on the bus even through the transfer may be between devices other than the data processor.
One prior art system utilizing a common electrical bus for coupling a plurality of units in a data processing system for transfer of information therebetween is shown in U.S. Pat. No. 4,030,075. Another is shown in U.S. Pat. No. 3,993,981. The manner and paths for transferring data in such systems, as well as the manner in which any one device may control data transfers, is dependent upon the implementation of the system; i.e., whether there is a common bus, whether the operation is synchronous or asynchronous, etc. The system's response and throughput are greatly dependent on the various structures.